In general, a data signal is transmitted in a unit of a frame having a predetermined format. A predetermined specific signal is inserted into the front of the data signal having such a frame format so that frame synchronization is performed on the receiving side.
For example, as shown in FIG. 6, the frame of a synchronization digital transmission system, such as an Optical Transport Network (OTN) used for an optical network, has a frame format in which a specific signal of a predetermined bit length, called a Frame Alignment Signal (FAS), is inserted into the front of the frame.
Some transmission apparatuses that deal with a data signal having such a frame format have a function of detecting error bits of a received data signal, and correcting the error bits (i.e., Forward Error Correction (FEC)). To perform a test, an error addition apparatus for adding errors to a data signal is being used.
FIG. 7 shows the configuration of a conventional error addition apparatus 10.
A data signal D configured to have the above frame format and outputted in, for example, an N-bit width (N is plural) from a data signal generation unit 5, and an error signal E (for example, a pseudo random signal) outputted in an N-bit width from an error signal generation unit 11 are inputted to an error addition unit 12. The error addition unit 12 adds errors, corresponding to the error signal E, to the data signal D and outputs a data signal D′ of an N-bit width.
Meanwhile, the data signal generation unit 5 and the error signal generation unit 11 receive, for example, a common clock (not shown) such that N-bit data outputted from the error signal generation unit 11 is synchronized with N-bit data of the data signal D outputted from the data signal generation unit 5.
Assuming that, for example, the N-bit data of the data signal D include d1 to dN and the N-bit data of the error signal E include e1 to eN, such error addition is performed by finding exclusive OR (EXOR) for each of pairs of bit data (d1,e1), (d2,e2), . . . , (dN,eN), and a result to which errors are added is outputted as the N-bit data signal D′.
Here, an output rate of the error signal E is set to be variable within a range less than an input rate of the data signal D under the control of a controller (not shown). A test for the FEC function of the target test apparatus is performed while changing the output rate of the error signal E. In the case in which a test for the target test apparatus is actually performed, the data signal D′ of an N-bit width is converted into serial data and then added to the target test apparatus.
Meanwhile, technology for adding errors to a data signal is disclosed in, for example, the Japanese Patent Laid-Open Publication No. 2002-330192.